1. Field of the Invention
The present invention relates to an automatic equalizer, and more particularly to a fully-digital-type automatic equalizer for use on the reception side of a digital radio communication system with multilevel quadrature amplitude modulation (multilevel QAM) or polarphase modulation.
2. Description of the Related Art
In recent years, digital radio communications systems have employed, on the reception side thereof, the equalizer with transversal filters for preventing the circuit quality from being deteriorated by frequency selective fading produced in propagation paths. Equalizers with greater equalizing capabilities include the decision feedback equalizer.
One conventional fully-digital-type 5-tap decision feedback equalizer is shown in FIG. 1 of the accompanying drawings. An analog baseband signal applied from a demodulator (not shown) to input terminal 1 is supplied to gain adjusting circuit 11. Gain adjusting circuit 11 compresses the signal with a compression ratio of 1/K (K &gt;1 or K=1) so that the level of the signal will not exceed the predetermined range of the input signal level of A/D converter 12 connected thereto even when the signal waveform is distorted due to fading in the propagation path. A/D converter 12 samples and quantizes the analog output signal from gain adjusting circuit 11 with clock signal CLK.sub.1 of sampling frequency f.sub.c supplied from terminal 2 and supplies N-bit digital signal train S.sub.1 to decision feedback transversal filter 101.
In decision feedback transversal filter 101, digital signal S.sub.1 is applied to first multiplier 25 and first delay circuit 21. First delay circuit 21 applies a delayed output signal to second multiplier 26 and second delay circuit 22. Second delay circuit 22 applies a delayed output signal to third multiplier 27. Decision circuit 14 applies an output signal to third delay circuit 23 whose delayed output signal is supplied to fourth multiplier 28 and fourth delay circuit 24. Fourth delay circuit 24 applies a delayed output signal to fifth multiplier 29. Multipliers 25, 26, 27 and delay circuits 21, 22 jointly constitute a circuit that is referred to as pre-equalizer 201, and multipliers 28, 29 and delay circuits 23, 24 jointly make up a circuit that is referred to as post-equalizer 202.
Each of delay circuits 21 through 24 comprises a flip-flop or the like and delays the supplied signal by one bit. In multipliers 25 through 29, each of the supplied input signals is multiplied by tap coefficients C.sub.-2, C.sub.-1, C.sub.0, C.sub.1, C.sub.2, respectively, supplied from control signal generator 102. The resultant products are supplied as multiplier output signals m.sub.-2, m.sub.-1, m.sub.0, m.sub.1, m.sub.2 to adder 13. Adder 13 digitally adds supplied multiplier output signals m.sub.-2, m.sub.-1, m.sub.0, m.sub.1, m.sub.2 and outputs equalized signal S.sub.1A, from which intersymbol interference due to fading contained in original signal S.sub.1 is removed, to post-processing circuit 15 and decision circuit 14. Decision circuit 14 determines an ideal signal level closest to the level of the supplied binary signal, and outputs a signal of the determined signal level as decision signal S.sub.1B. As a result, since post-equalizer 202 is supplied with decision signal S.sub.1B from which waveform distortion due to fading or the like has been removed, intersymbol interference that can be removed by post-equalizer 202 is completely equalized unless the tap coefficients supplied to multiplier 28, 29 are accurate and the multiplier output signals are saturated. Post-processing circuit 15 is used to restore the original signal, which has been compressed to 1/K by gain adjusting circuit 11, back to the original level, and outputs a signal with the properly corrected level from terminal 3.
Operation of decision circuit 14 and post-processing circuit 15 will be described in specific detail with reference to FIG. 2 of the accompanying drawings. It is assumed that the input signal applied to the terminal 1 is a 4-valued signal which is a baseband signal modulated according to 16-valued quadrature amplitude modulation (16QAM). The ideal values of the 4-valued signal have levels indicated by white dots A, B, C, D (FIG. 2) as the input signal applied to A/D converter 12, white dots A. B, C, D corresponding to 2-bit information signals (00), (01), (10), (11), respectively, each composed of the first and second bits when the compression ratio is 1. Third or greater bits of the output signal from A/D converter 12 are an error signal indicating a deviation from the ideal values. If compression ratio 1/K is 1/2, then dots A, B, C, D are reduced in amplitude to half, and compressed to respective black dots A.sub.1, B.sub.1, C.sub.1, D.sub.1. The ideal values of dots A.sub.1, B.sub.1, C.sub.1, D.sub.1 are represented by 3-bit signals (010), (011), (100), (101), respectively. Then, fourth or greater bits of the output signal from A/D converter 12 are an error signal indicating a deviation from the ideal values. Inasmuch as equalized output signal S.sub.1A from decision feedback transversal filter 101 contains thermal noise and intersymbol interference that cannot be removed, the error signal varies at random. Therefore, if first- through Nth-bit signals were fed back directly to post-equalizer 202, the signal could not be appropriately equalized since the input signals to post-equalizer 202 contain errors. To solve the above problem, decision circuit 14 uniquely determines the first through third bits to be any one of four ideal values 010, 011, 100, 101 and also determines the fourth and greater bits to be fixed value 100.about.0(.about. indicates all 0) according to the output signal of the decision circuit shown in FIG. 2 when digital signal S.sub.1A is inputted, thereby producing decision signal S.sub.1B. If N =5, then when digital signal S.sub.1A =10011 is inputted, decision signal S.sub.1B =10010 is produced, and when digital signal S.sub.1A =11100 is inputted, decision signal S.sub.1B =10110 is produced. To double the 1/2-compressed signal into the original signal, post-processing circuit 15 converts the supplied signal according to the output signal from the post-processing circuit shown in FIG. 2, thereby producing 3-bit signals of path 1, path 2 and path 3. For example, when digital signal S.sub.1A =10011 is inputted, post-processing circuit 15 produces output signal D=101, and when digital signal S.sub.1A =11100 is inputted, post-processing circuit 15 produces output signal D= 111. Paths 1, 2 are information bits, and path 3 is an error bit indicating the polarity of the error signal. Tap coefficients C.sub.-2, C.sub.-1, C.sub.0, C.sub.1, C.sub.2 are obtained from control signal generator 102 which operates exclusive-OR calculations between polarity signal d (path 1) indicative of the polarity of the received signal and error signal e (path 3), averages the result over time and outputs the averaged output. The principles of generating the tap coefficients are described in detail, for example, in Chapter 11 of "Digital Signal Processing" edited and published by the Institute of Electronics, Information and Communication Engineering, 1975 in Japan
FIG. 3 of the accompanying drawings illustrates an instance of two-ray fading to which the two-ray fading equalizing characteristic of the above conventional decision feedback equalizer is applied. Curve S shown in FIG. 3 is also referred to as a signature curve. The graph of FIG. 3 has a horizontal axis representing notch position fd which indicates the shift of the fading notch frequency from the center of the spectrum of a desired signal, the shift being normalized by the clock frequency, and a vertical axis representing amplitude ratios .rho. which indicate amplitudes of the reflected wave (delayed wave) normalized by amplitudes of the principal wave. Notch depth Dn is expressed by Dn=-20 log (1-.rho.)dB. Using notch position fd and amplitude ratio .rho. as parameters, curve S is plotted by interconnecting points fd and .rho. where error ratio P=1.times.10.sup.-4. Error ratio P is greater than 10.sup.-4 in the area that is surrounded by curve S in FIG. 3 Therefore, it can be understood that the smaller the area surrounded by curve S, the greater the ability of the equalizer. In the range 0&lt;.rho.&lt;1, since the interference wave is delayed with respect to the principal wave, intersymbol interference is removed by the post-equalizer. In the range of .rho.&gt;1, intersymbol interference is removed by the pre-equalizer 201 as the delayed wave becomes the principal wave. In the decision feedback equalizer, the input signal applied to the post-equalizer is an equalized decision signal and its value is substantially the same as the ideal value. Therefore, the signal is equalized substantially completely in the range 0&lt;.rho.&lt;1 in FIG. 3. In the range .rho.&gt;1, inasmuch as intersymbol interference is not removed from the input signal applied to the pre-equalizer, the equalizing ability is lower than in the range 0&lt;.rho.&lt;1. The input level, the tap coefficients, and the output level of the multipliers in the pre- and post-equalizers have values ranging from notch position -1 to notch position +1.
With the conventional decision feedback equalizer described above, since the improving capability is not good in the range .rho.&gt;1 in which the delayed wave is more intensive than the principal wave, as indicated by signature curve S in FIG. 3, the outage probability is not effectively improved in a digital microwave communications system in which the conditions .rho.&lt;1 and .rho.&gt;1 occur with substantially equal probability.